解光军教授于2009年在世界计算机科学与信息工程进展会议发表的论文"An all-digital PLL for video pixel clock regeneration applications"[1]近日被国际顶级期刊IEEE Journal of Solid-State Circuit（JSSC）2011年第10期刊登的论文[2]引用，该论文作者来自台湾成功大学，题为"A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology"，作者在文中提到"An ADPLL with a low bandwidth can reduce the period jitter, but the tracking jitter is increased due to the slow response to the reference clock edge variations. As a result, in ADPLLs [15]–[17], two-PLL architecture is used with an external oscillator as a precise timing reference to generate a very high speed sampling clock. "[2]中提及的文献[15]即为本实验室发表论文[1]。

附：

[1] G.-J. Xie and C.Wang, "An all-digital PLL for video pixel clock regeneration applications," in Proc. 2009 World Congress Computer Science and Information Engineering (CSIE), Mar. 2009, pp. 392–396.

[2] C.-C. Chung and C.-Y. Ko, "A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology," IEEE J. Solid-State Circuits, vol. 46, no. 10, pp. 2300–2311, Oct. 2011.